include JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a .

interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, a.

......... 3 SHARC Family Core Architecture ........ 4 Family Peripheral Architecture .. 7 I/O Processor Features . 10 System Design .. 10 Development Tools ..... 11 Additional Information 12 Related Signal Chains .. 12 Pin Function Descriptions .....

ADSP-21362

ADSP-21363

ADSP-21364

ADSP-21365

ADSP-21366

ADSP-21367

ADSP-21368

ADSP-21371

ADSP-21375

ADSP-2100A

ADSP-2101

ADSP-21020

ADSP-2103